In the manufacture of semiconductor products such as integrated circuits, individual electrical components are formed on or in a semiconductor substrate, and are thereafter interconnected to form electrical circuits. Interconnection of these components within a semiconductor device is typically accomplished by forming a multi-level interconnect network structure in layers formed over the electrical components, sometimes referred to as metalization, by which the device active elements are connected to other devices to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching openings for vias and/or trenches. Conductive material, such as copper or tungsten is then formed in the openings to form inter-layer contacts and interconnect routing structures.
In forming a single metalization level or layer, a dielectric material is typically deposited over a previous metalization level, and the dielectric is selectively etched to form openings at predefined locations that extend through the dielectric to the underlying metalization level. Copper is then deposited, which fills the openings and covers the entire dielectric of the current level. After copper deposition, the wafer is planarized using chemical mechanical polishing (CMP) to expose portions of the dielectric between the copper-filled openings. At this point in the process, it is desirable to inspect the wafer to ascertain the quality and integrity of the interconnect structures, using measurement equipment and techniques referred to as metrology operations. For instance, it is desirable to measure trench widths and copper feature resistivity, and to perform other defect analysis and electrical parameter tests, in order to separate out defective wafers and avoid the cost of further processing those wafers that will not meet final product quality standards. Often, such metrology takes 8-12 hours, wherein reducing the amount of metrology after CMP risks missing an early detection of defects in the metalization structures.
However, the planarization exposes the upper surfaces of the copper-filled trenches and vias to moisture and other corrosive ambient conditions, particularly where the planarized wafers are transferred from instrument to instrument to perform the desired metrology operations. Such corrosive ambient conditions cause oxidation and other degradation of the copper, leading to increased contact resistance and adhesion problems in subsequent fabrication processing. Corrosion of copper interconnect structures is detrimental to interconnect isolation integrity, and can lead to interconnect leakage between copper structures in a single metalization level, as well as premature dielectric breakdown (e.g., reduced breakdown voltage withstanding capacity). In this regard, conductive metal diffusion barriers are typically formed in the dielectric trench or via openings to prevent out-diffusion of the subsequently deposited copper. After planarization, oxidation occurs rapidly at the junction of the dissimilar metals (the copper and the barrier metal) along the edges of the exposed conductive interconnect structure. The corrosion tends to migrate outward from the edges of the structure, thereby reducing the isolation distance between adjacent conductive features, by which the likelihood of detrimental intra-level dielectric breakdown is increased.
Efforts have been made to alleviate the copper corrosion by coating the polished wafer with an organic benzotriazole (BTA) layer prior to performing metrology operations. However, BTA coatings tend to evaporate and the corrosion protection typically only lasts for 3-6 hours. This process time window for making measurements of the planarized wafer is insufficient to allow the full range of metrology operations desired to effectively sort out defective wafers, where a longer process window of up to 12 hours or more is desirable. Also, the use of BTA requires a separate cleaning step after the metrology to remove any remaining BTA. Another approach involves depositing an etch-stop layer material over the planarized wafer prior to metrology. However, many metrology operations employ non-contacting measurement instruments, such as laser based physical defect detection tools, secondary electron microscopes, resistivity measuring laser tools and the like which do not cause physical harm to the wafer, but whose measurement capabilities are best utilized when the measured features and structures are conductive. While the exposed copper surfaces on the wafer are conductive, the etch-stop materials are typically non-conductive (e.g., silicon nitride or silicon carbide). Thus, while forming the etch-stop layer prior to metrology may inhibit unwanted copper corrosion, this approach inhibits the ability to obtain proper metrology measurements. Accordingly, there remains a need for improved techniques for protecting copper structures from corrosion while facilitating in-line metrology measurements in the manufacture of semiconductor devices.